VIPER28

Operation descriptions

23/29

Equation 7

Equation 8

page 8

.

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 24. FB pin configuration

Figure 25. FB pin configuration

()

1

FB

)

DYN

(

FB

FB

1

FB

)

DYN

(

FB

PFB

R

R

C

2

R

R

f

⋅

⋅

⋅

π

⋅

+

=

()

)

DYN

(

FB

1

FB

1

FB

1

PFB

R

R

C

2

1

f

+

⋅

⋅

π

⋅

=

From sense FET

4.8V

BURST

PWM

CONTROL

Cfb

To PWM Logic

BURST-MODE

REFERENCES

BURST-MODE

LOGIC

+

-

PWM

+

-

OLP comparator

To disable logic

4.8V

From sense FET

PWM

CONTROL

+

-

PWM

BURST

To disable logic

+

-

OLP comparator

To PWM Logic

BURST-MODE

LOGIC

Cfb1

Rfb1

Cfb

BURST-MODE

REFERENCES