M34D64-W

Device operation

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Figure 9.

Read mode sequences

1.

must be identical.

3.10

Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

3.11

Random Address Read

A dummy Write is performed to load the address into the address counter (as shown in

Figure 9.: Read mode sequences) but without sending a Stop condition. Then, the bus

master sends another Start condition, and repeats the Device Select Code, with the

Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the

addressed byte. The bus master must not acknowledge the byte, and terminates the transfer

with a Stop condition.

Dev sel *

Byte addr

Byte addr

Dev sel

Data out 1

AI01105d

Data out N

Current

Address

Read

Dev sel

Data out

Random

Address

Read

Dev sel *

Data out

Sequential

Current

Read

Data out N

Dev sel *

Byte addr

Byte addr

Sequential

Random

Read

Dev sel *

Data out 1

ACK

R/W

NO ACK

ACK

R/W

ACK

ACK

ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

ACK

ACK

ACK

R/W

ACK

ACK

R/W

ACK

NO ACK