L6566B datasheet(32/51 Pages) STMICROELECTRONICS

32 / 51 page

Application information

L6566B

32/51

Equation 9

which is the parameter that the amplitude of the generated side-band harmonics depends

on.

The minimum frequency fsw_min (occurring on the peak of the triangle) and the maximum

frequency fsw_max (occurring on the valley of the triangle) will be symmetrically placed

around the centre value fsw, so that:

Equation 10

Then, RT will be found from (5) (see Section 5.2: Zero current detection and triggering block;

oscillator block on page 21

), while RMOD and CMOD can be calculated as follows:

Equation 11

where

∆f

sw and fm (in kHz, with CMOD in nF and RMOD in kΩ) will be selected by the user so

to achieve the best compromise between attenuation of peak EMI emissions and clean

converter operation.

5.9

Latched disable function

The device is equipped with a comparator having the non-inverting input externally available

at the pin DIS (8) and with the inverting input internally referenced to 4.5 V. As the voltage

on the pin exceeds the internal threshold, the device is immediately shut down and its

consumption reduced to a low value.

The information is latched and it is necessary to let the voltage on the Vcc pin go below the

UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long

as the converter is connected to the input source, the HV generator is activated periodically

so that Vcc oscillates between the start-up threshold VccON and VccON - 0.5 V. Activating the

HV generator in this way cuts its power dissipation approximately by three (as compared to

the case of continuous conduction) and keeps peak silicon temperature close to the average

value.

To let the L6566B restart it is then necessary to disconnect the converter from the input

source. Pulling pin 16 (AC_OK) below the disable threshold (see Section 5.12: Brownout

protection on page 37

) will stop the HV generator until Vcc falls below Vccrestart, so that the

latch can be cleared and a quicker restart is allowed as the input source is removed. This

operation is shown in the timing diagram of Figure 20 on page 33.

∆

max

min

;

∆

−

MOD

∆

⋅

MOD

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