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6V7 数据表(PDF) 21 Page - Renesas Technology Corp |
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6V7 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 298 page  Rev.1.00 May 18, 2004 page 21 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP Figure 2.3.3 Device’s internal status after a reset is cleared (1) X : Nothing is mapped to this bit ? : Undefined (000416)··· Processor mode register 0 (Note) 0016 (000516)··· Processor mode register 1 0 0 0 (000616)··· System clock control register 0 (000716)··· System clock control register 1 (000916)··· Address match interrupt enable register 0 0 Protect register (000A16)··· 00 0 (000F16)··· Watchdog timer control register 0 0? 0? ? ? ? (001416)··· Address match interrupt register 1 (001516)··· (001616)··· 0 0016 0016 0 0 0 (002C16)··· DMA0 control register 0 0 0 0 0 ? 0 0 (003C16)··· DMA1 control register 0 0 0 0 0 ? 0 0 (001016)··· Address match interrupt register 0 (001116)··· (001216)··· 0 0016 0016 0 0 0 (004416)··· OSD1 interrupt control register ? 0 0 0 (004816)··· OSD2 interrupt control register ?000 4816 2016 0 0 0 (004B16)··· DMA0 interrupt control register ? 0 0 0 (004C16)··· DMA1 interrupt control register ? 0 0 0 (004A16)··· Bus collision detection interrupt control register 0 0 0 ? UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register Data slicer 0 interrupt control register VSYNC interrupt control register (004F16)··· (005016)··· (005116)··· (005216)··· (005316)··· (005416)··· ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register (005516)··· (005616)··· (005716)··· (005816)··· (005916)··· ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 A-D conversion interrupt control register (004E16)··· ? 0 0 0 Multi-master I2C-BUS interface 0 interrupt control register (004D16)··· ? 0 0 0 0 (004916)··· Multi-master I2C-BUS interface 1 interrupt control register ?000 00 Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register (005A16)··· (005B16)··· ? 0 0 0 ? 0 0 0 (005C16)··· ? 0 0 0 (005D16)··· ? 00 0 00 (005E16)··· ? 00 0 00 Clock control register I/O polarity control register Horizontal position register OSD control register 1 OSD control register 3 OSD control register 2 Raster color register (020516)··· 0016 8016 (020616)··· 0016 (020316)··· 0016 (020416)··· 0016 (020216)··· 0016 (020716)··· (020816)··· 0016 Left border control register Right border control register (027016)··· (027216)··· (027316)··· 0016 0116 (027116)··· 0 00 0 00 SPRITE OSD control register (020116)··· 0 00 0 0 (020916)··· 0016 OSD reserved register 3 HSYNC counter register Peripheral mode register (027B16)··· (027E16)··· (027D16)··· 0 0 0 00 00 0 0 0 0016 OSD reserved register 4 (027A16)··· 0 0 00 0 00 OSD reserved register 2 (027C16)··· 0016 Data slicer 0 control register 1 Data slicer 0 control register 2 Caption position register 0 OSD control register 4 (026016)··· 0016 (026116)··· 0 00 (026616)··· ? ?? ? ? 0 00 ? 00 0 0 0 0 0 00 ? ? ? ?? 00 (025F16)··· 0 0 OSD reserved register 1 (025D16)··· 0016 Clock run-in detect register 0 Data clock position register 0 (026916)··· (026A16)··· 0 0 01 0 Slice standard voltade selection register (026716)··· 0016 Data slicer 0 reserved register 1 (026816)··· 0016 The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. (000816)··· Chip select control register 0116 (004516)··· ? 0 0 0 Data slicer 1 interrupt control register OSD reserved register 5 (020A16)··· 0016 OSD reserved register 6 (020B16)··· 0016 (026B16)··· 0016 (026C16)··· ? ? ? ? ??? ? ? ? ???? (026D16)··· (026E16)··· 0016 (026F16)··· ID1 control register 0 CRCC data register 0 Test reserved register 0 Reserved register Standard clock detection register 0 0 |
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