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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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6V7 数据表(PDF) 30 Page - Renesas Technology Corp |
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6V7 数据表(HTML) 30 Page - Renesas Technology Corp |
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30 / 298 page  Rev.1.00 May 18, 2004 page 30 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP Figure 2.4.4 Chip select control register _____ ______ ________ Table 2.4.5 Operation of RD, WR, and BHE signals (3) Read/write signals With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select _____ ________ ______ _____ ________ _________ the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus _____ ______ _______ (BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 2.4.4 and 2.4.5 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically se- lected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. W Function Bit symbol Bit name Chip select control register Symbol Address When reset CSR 000816 0116 R b7 b6 b5 b4 b3 b2 b1 b0 CS1 CS0 CS3 CS2 CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit CS1W CS0W CS3W CS2W CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled 0 : Wait state inserted 1 : No wait state Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses WRH WRL RD Data bus width 16-bit (BYTE = “L”) H H H H L H L H H L L L Status of external data bus RD BHE WR HL L LH L HL H LH H Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Data bus width A0 H H L L HL L L LH L L H L H / L L H H / L 8-bit (BYTE = “H”) Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data 16-bit (BYTE = “L”) Not used Not used _____ ________ _________ Table 2.4.4 Operation of RD, WRL, and WRH signals |
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