M38039G8HKP datasheet(19/92 Pages) RENESAS

19 / 92 page

Rev.1.10

Nov 14, 2005

Page 19 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 13. Port block diagram (2)

(13) Port P50

(12) Port P47

(9) Port P37

(14) Port P51

(10) Port P40

(11) Port P41

INT40 Interrupt input

Serial I/O3 mode selection bit

Serial I/O3 ready output

Serial I/O3 enable bit

Pull-up control bit

Data bus

Port latch

Direction

SRDY3 output enable bit

Port XC switch bit

Pull-up control bit

Data bus

Port latch

Direction

Port XC

switch bit

INT00 Interrupt input

Port XC switch bit

Pull-up control bit

Data bus

Port latch

Direction

Sub-clock generating circuit input

Timer output

CNTR2 interrupt input

Pull-up control bit

Data bus

Port latch

Direction

Serial I/O2 output

Pull-up control bit

Data bus

Port latch

Direction

Serial I/O2 transmit completion signal

Serial I/O2 port selection bit

Pull-up control bit

Data bus

Port latch

Direction

Serial I/O2 input

Serial I/O1 mode selection bit

Serial I/O1 enable bit

SRDY1 output enable bit

Bit 2

Bit 1

Bit 0

Timer Z operating

mode bits

Serial I/O1 ready output

P-channel

output

disable bit

Port XC

switch bit

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