R8CSLASH2G datasheet(4/43 Pages) RENESAS

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R8C/2G Group

1. Overview

Rev.1.00

Apr 04, 2008

Page 4 of 41

REJ03B0223-0100

1.3

Block Diagram

Figure 1.2 shows a Block Diagram.

Figure 1.2

Block Diagram

R8C/Tiny Series CPU core

Memory

Watchdog timer

(15 bits)

ROM(1)

RAM(2)

Multiplier

R0H

R0L

R1H

R1L

USP

ISP

INTB

FLG

I/O ports

NOTES:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

System clock

generation circuit

High-speed on-chip oscillator

Low-Speed on-chip oscillator

XCIN-XCOUT

Timers

Timer RA (8 bits)

Timer RB (8 bits)

Timer RE (8 bits)

Timer RF (16 bits)

UART or

clock synchronous serial I/O

(8 bits

× 2 channels)

LIN module

(1 channel)

Port P0

Port P1

Port P3

Port P4

Port P6

Peripheral functions

Voltage detection circuit

(3 circuits)

Comparator

(2 circuits)

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