R8CSLASH2G datasheet(27/43 Pages) RENESAS

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R8C/2G Group

5. Electrical Characteristics

Rev.1.00

Apr 04, 2008

Page 27 of 41

REJ03B0223-0100

NOTES:

The measurement condition is Topr =

−20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

This condition (external power VCC rise gradient) does not apply if VCC

≥ 1.0 V.

To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the

VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.

tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on

reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if

−20°C ≤ Topr ≤ 85°C, maintain tw(por1) for

3,000 s or more if

−40°C ≤ Topr < −20°C.

Figure 5.2

Reset Circuit Electrical Characteristics

Table 5.7

Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)

Symbol

Parameter

Condition

Standard

Unit

Min.

Typ.

Max.

Vpor1

Power-on reset valid voltage(4)

−−

0.1

Vpor2

Power-on reset or voltage monitor 0 reset valid

voltage

−

Vdet0

trth

External power VCC rise gradient(2)

−−

mV/msec

NOTES:

1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage

range (2.2 V or above) during the sampling time.

2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.

3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of Hardware Manual for details.

Vdet0(3)

Vpor1

Internal

reset signal

(“L” valid)

tw(por1)

Sampling time(1, 2)

Vdet0(3)

fOCO-S

× 32

fOCO-S

× 32

Vpor2

External

Power VCC

trth

2.2 V

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