M62320GP

REJ03D0909-0100 Rev.1.00 Mar 25, 2008

Page 4 of 10

I

Limits

Item

Symbol

Min

Max

Unit

SCL clock frequency

0

100

kHz

Free time: the bus must be free before a new transmission can start

4.7

—

μs

Hold time START Condition

After this period, the first clock pulse is generated.

4.0

—

μs

Low period of the clock

4.7

—

μs

High period of the clock

4.0

—

μs

Set-up time for START condition

Only relevant for a repeated START condition

4.7

—

μs

Data Hold time

0

—

μs

Data Set-up time

250

—

ns

Rise time of SDA and SCL signals

—

1000

ns

Fall time of SDA and SCL signals

—

300

ns

Set-up time for STOP condition

4.0

—

μs

Note:

Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling

edge of SCL.

Timing Chart

Start

Start

Start

Stop

SDA

SCL