M62320GP

REJ03D0909-0100 Rev.1.00 Mar 25, 2008

Page 6 of 10

Digital Data Format

1. Write mode: I

First

Last

S

Slave address

W

A

I/O setting

A

8-bit data

A

8-bit data

A

…..

AP

2. Read mode: Parallel data input to I

First

Last

S

Slave address

W

A

8-bit data

A

8-bit data

A

8-bit data

A

…..

8-bit data

A

P

Transmission from Master (MCU etc.) to Slave (M62320GP)

Transmission from Slave (M62320GP) to Master (MCU etc.)

• S: Start condition

While SCL level is high, SDA line level should be changed from high to low.

• Slave address

Chip select data

MSB

LSB

A2

A1

A0

CS2

CS1

CS0

0

1

1

1

A2

A1

A0

First

MSB

Last

LSB

0

0

0

L

L

L

0

0

1

L

L

H

0

1

0

L

H

L

:

:

:

:

:

:

1

1

1

H

H

H

Note:

Lower three bits (A0, A1, A2) are a programmable

address. This IC is accessed only when the lower 3

bits data of slave address coincide with the data of

CS0 to CS2. (refer to the right table)

Note: L = Low, H = High

• W: Write (SDA = Low), R: Read (SDA = High)

• A: Acknowledge bit

• I/O setting data (I/O setting of parallel data I/O terminals.)

P7

P1

P6

P5

P4

P3

P2

First

MSB

Last

LSB

P0

Note:

DATA INPUT from parallel data terminals = Low

DATA OUTPUT to parallel data terminals = High

Each bit data corresponds to the I/O state of the parallel data terminals.

• 8-bit data

D7

D1

D6

D5

D4

D3

D2

First

MSB

Last

LSB

D0

• P: Stop condition

While SCL level is high, SDA level should be changed from low to high.