M38041FEHKP datasheet(67/116 Pages) RENESAS

67 / 116 page

Rev.1.01

Jan 25, 2005

page 67 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

[I2C START/STOP Condition Control Register

(S2D)] 001616

The I2C START/STOP condition control register (S2D: address

001616) controls START/STOP condition detection.

•Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0)

SCL release time, setup time, and hold time change the detection

condition by value of the main clock divide ratio selection bit and

the oscillation frequency f(XIN) because these time are measured

by the internal system clock. Accordingly, set the proper value to

the START/STOP condition set bits (SSC4 to SSC0) in considered

of the system clock frequency. Refer to Table 11.

Do not set “000002” or an odd number to the START/STOP condi-

tion set bits (SSC4 to SSC0).

Refer to Table 12, the recommended set value to START/STOP

condition set bits (SSC4–SSC0) for each oscillation frequency.

•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)

An interrupt can occur when detecting the falling or rising edge of

the SCL or SDA pin. This bit selects the polarity of the SCL or SDA

pin interrupt pin.

•Bit 6: SCL/SDA interrupt pin selection bit (SIS)

This bit selects the pin of which interrupt becomes valid between

the SCL pin and the SDA pin.

Note: When changing the setting of the SCL/SDA interrupt pin polarity se-

lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS

interface enable bit ES0, the SCL/SDA interrupt request bit may be

set. When selecting the SCL/SDA interrupt source, disable the inter-

rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/

SDA interrupt pin selection bit, or the I2C-BUS interface enable bit

ES0 is set. Reset the request bit to “0” after setting these bits, and

enable the interrupt.

START/STOP

condition

control register

Oscillation

frequency

f(XIN) (MHz)

Fig. 66 Structure of I2C START/STOP condition control register

Note: Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and “000002”.

Table 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency

Main clock

divide ratio

Internal

clock

(MHz)

SCL release time

(

µs)

Setup time

(

µs)

Hold time

(

µs)

XXX11010

XXX11000

XXX00100

XXX01100

XXX01010

XXX00100

3.5

µs (14 cycles)

3.25

µs (13 cycles)

3.0

µs (3 cycles)

3.5

µs (7 cycles)

3.0

µs (6 cycles)

3.0

µs (3 cycles)

6.75

µs (27 cycles)

6.25

µs (25 cycles)

5.0

µs (5 cycles)

6.5

µs (13 cycles)

5.5

µs (11 cycles)

5.0

µs (5 cycles)

3.25

µs (13 cycles)

3.0

µs (12 cycles)

2.0

µs (2 cycles)

3.0

µs (6 cycles)

2.5

µs (5 cycles)

2.0

µs (2 cycles)

b7b0

I2C START/STOP condition

control register

START/STOP condition set bits

SCL/SDA interrupt pin polarity

selection bit

0 :Falling edge active

1 :Rising edge active

SCL/SDA interrupt pin selection bit

0 :SDA valid

1 :SCL valid

Not used

(Fix this bit to “0”.)

SIS SIP SSC4SSC3SSC2SSC1SSC0

(S2D : address 001616)

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