M38041FEHKP datasheet(15/116 Pages) RENESAS

15 / 116 page

Rev.1.01

Jan 25, 2005

page 15 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

Fig. 12 Port block diagram (1)

(6) Ports P34, P44

Serial I/O input

(1) Ports P0, P6

A/D converter input

Analog input pin

selection bit

Direction

Data bus

Port latch

Pull-up control bit

(2) Ports P10, P11, P42, P43, P57

Interrupt input

(3) Ports P12 to P17, P2

(4) Ports P30, P31

DA1 output enable (P30)

DA2 output enable (P31)

(8) Ports P36, P46

(7) Ports P35, P45

(5) Ports P32, P33

Data bus

Direction

Port latch

Pull-up control bit

Direction

Port latch

Data bus

Direction

Port latch

Pull-up control bit

D/A converter output

Data bus

Direction

Port latch

Pull-up control bit

Serial I/O enable bit

Receive enable bit

Direction

Port latch

Data bus

Pull-up control bit

Serial I/O enable bit

Transmit enable bit

P-channel output

disable bit

Serial I/O enable bit

Serial I/O mode selection bit

Serial I/O enable bit

Serial I/O synchronous clock

selection bit

Data bus

Direction

Port latch

Pull-up control bit

Serial I/O external clock input

Serial I/O clock output

Serial I/O output

Direction

Port latch

Data bus

SDA output

SCL output

SDA input

SCL input

I2C-BUS interface enable bit

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