M38042FEHKP datasheet(62/116 Pages) RENESAS

62 / 116 page

Rev.1.01

Jan 25, 2005

page 62 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

Fig. 59 Structure of I2C control register

[I2C Control Register (S1D)] 001416

The I2C control register (S1D: address 001416) controls data com-

munication format.

•Bits 0 to 2: Bit counter (BC0–BC2)

These bits decide the number of bits for the next 1-byte data to be

transmitted. The I2C interrupt request signal occurs immediately

after the number of count specified with these bits (ACK clock is

added to the number of count when ACK clock is selected by ACK

clock bit (bit 7 of S2, address 001516) have been transferred, and

BC0 to BC2 are returned to “0002”.

Also when a START condition is received, these bits become

“0002” and the address data is always transmitted and received in

8 bits.

•Bit 3: I2C interface enable bit (ES0)

This bit enables to use the multi-master I2C-BUS interface. When

this bit is set to “0,” the use disable status is provided, so that the

SDA and the SCL become high-impedance. When the bit is set to

“1,” use of the interface is enabled.

When ES0 = “0,” the following is performed.

• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C

status register, S1, at address 001316 ).

• Writing data to the I2C data shift register (S0: address 001116) is

disabled.

•Bit 4: Data format selection bit (ALS)

This bit decides whether or not to recognize slave addresses.

When this bit is set to “0,” the addressing format is selected, so

that address data is recognized. When a match is found between

a slave address and address data as a result of comparison or

when a general call (refer to “I2C Status Register,” bit 1) is re-

ceived, transfer processing can be performed. When this bit is set

to “1,” the free data format is selected, so that slave addresses are

not recognized.

•Bit 5: Addressing format selection bit (10BIT SAD)

This bit selects a slave address specification format. When this bit

is set to “0,” the 7-bit addressing format is selected. In this case,

only the high-order 7 bits (slave address) of the I2C slave address

registers 0 to 2 are compared with address data. When this bit is

set to “1,” the 10-bit addressing format is selected, and all the bits

of the I2C slave address registers 0 to 2 are compared with ad-

dress data.

•Bit 7: I2C-BUS interface pin input level selection bit (TISS)

This bit selects the input level of the SCL and SDA pins of the

multi-master I2C-BUS interface.

TISS

10 BIT

SAD

ALS ES0 BC2 BC1 BC0

Not used

(return “0” when read)

I2C control register

(S1D : address 001416)

Bit counter (Number of

transmit/receive bits)

b2b1b0

0 : 8

1 : 7

0 : 6

1 : 5

0 : 4

1 : 3

0 : 2

1 : 1

I2C-BUS interface

enable bit

0 : Disabled

1 : Enabled

Data format selection bit

0 : Addressing format

1 : Free data format

Addressing format

selection bit

0 : 7-bit addressing

format

1 : 10-bit addressing

format

I2C-BUS interface pin input

level selection bit

0 : CMOS input

1 : SMBUS input

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