M38042FEHKP datasheet(65/116 Pages) RENESAS

65 / 116 page

Rev.1.01

Jan 25, 2005

page 65 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

START Condition Generating Method

When writing “1” to the MST, TRX, and BB bits of the I2C status

slave address to the I2C data shift register (S0: address 001116)

with the condition in which the ES0 bit of the I2C control register

(S1D: address 001416) is “1” and the BB flag is “0”, a START con-

dition occurs. After that, the bit counter becomes “0002” and an

SCL for 1 byte is output. The START condition generating timing is

different in the standard clock mode and the high-speed clock

mode. Refer to Figure 62, the START condition generating timing

diagram, and Table 9, the START condition generating timing

table.

STOP Condition Generating Method

When the ES0 bit of the I2C control register (S1D: address

001416) is “1,” write “1” to the MST and TRX bits, and write “0” to

the BB bit of the I2C status register (S1: address 001316) simulta-

neously. Then a STOP condition occurs. The STOP condition

generating timing is different in the standard clock mode and the

high-speed clock mode. Refer to Figure 63, the STOP condition

generating timing diagram, and Table 10, the STOP condition gen-

erating timing table.

Fig. 62 START condition generating timing diagram

Fig. 63 STOP condition generating timing diagram

Table 10 STOP condition generating timing table

Item

Setup time

Hold time

Standard clock mode

5.0

µs (20 cycles)

4.5

µs (18 cycles)

Note: Absolute time at

φ = 4 MHz. The value in parentheses denotes the

number of

φ cycles.

High-speed clock mode

3.0

µs (12 cycles)

2.5

µs (10 cycles)

Table 9 START condition generating timing table

Item

Setup time

Hold time

Standard clock mode

5.0

µs (20 cycles)

5.0

µs (20 cycles)

Note: Absolute time at

φ = 4 MHz. The value in parentheses denotes the

number of

φ cycles.

High-speed clock mode

2.5

µs (10 cycles)

2.5

µs (10 cycles)

I2C status register

write signal

Hold time

Setup

time

SCL

SDA

I2C status register

write signal

Hold time

Setup

time

SCL

SDA

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