HD151TS206SS

Rev.1.00, Apr.28.2003, page 13 of 34

I

Byte12 Control Register

Bit

Description

Contents

Type

Default

Note

7

Reserved

RW

0

6

Reserved

RW

0

5

Reserved

RW

0

4

Reserved

RW

0

3

Reserved

RW

0

2

PLL1 Output (VCO1)

Frequency Control Bit

(M1/N1 Divider Control Bit)

PLL1 : for

SRC/3V66/PCI_PLL

0 = Normal mode

PLL1 M1[6:0] and N1[9:0] are changed

on Table 5 selection decided by

FS4/3/2/A/B or B9[5:1]

1 = Over or Down clocking mode

PLL1 M1[6:0] and N1[9:0] are changed

by B12[1:0] , B13[7:0] and B14[6:0].

B12[1:0] ,B13[7:0] and B14[6:0] are

able to be changed at B12[2] = 1.

RW

0

1

PLL1 N1 Divider Control Bit9

N1[9]

RW

0

0

PLL1 N1 Divider Control Bit8

N1[8]

RW

0

See

Note1

Note:

1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.

Byte13 Control Register

Bit

Description

Contents

Type

Default

Note

7

PLL1 N1 Divider Control Bit7

N1[7]

R/W

0

6

PLL1 N1 Divider Control Bit6

N1[6]

R/W

1

5

PLL1 N1 Divider Control Bit5

N1[5]

R/W

0

4

PLL1 N1 Divider Control Bit4

N1[4]

R/W

0

3

PLL1 N1 Divider Control Bit3

N1[3]

R/W

1

2

PLL1 N1 Divider Control Bit2

N1[2]

R/W

0

1

PLL1 N1 Divider Control Bit1

N1[1]

R/W

1

0

PLL1 N1 Divider Control Bit0

N1[0]

R/W

1

See

Note1

Note:

1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.

Byte14 Control Register

Bit

Description

Contents

Type

Default

Note

7

Reserved

R/W

0

6

PLL1 M1 Divider Control Bit6

M1[6]

R/W

0

5

PLL1 M1 Divider Control Bit5

M1[5]

R/W

0

4

PLL1 M1 Divider Control Bit4

M1[4]

R/W

1

3

PLL1 M1 Divider Control Bit3

M1[3]

R/W

0

2

PLL1 M1 Divider Control Bit2

M1[2]

R/W

0

1

PLL1 M1 Divider Control Bit1

M1[1]

R/W

1

0

PLL1 M1 Divider Control Bit0

M1[0]

R/W

0

See

Note1

Note:

1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.