HD151TS206SS datasheet(21/34 Pages) RENESAS

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HD151TS206SS

Rev.1.00, Apr.28.2003, page 21 of 34

Clock Stop Timing Diagram

2× Iref (Controled by Byte2[5:3])

PWRDWN#

CPU (Stoppable)

CPU# (Stoppable)

CPU (Stoppable)

PWRDWN# Assertion/De-assersion

PWRDWN# Assertion/De-assertion Waveforms

6× Iref

< 1.8 ms

PWRDWN#

PWRDWN# Functionality

CPU#

CPU

SRC

SRC#

3V66

66MHz

Normal Normal Normal

Float

Low

PCIF/PCI

33MHz

Low

USB/DOT

48MHz

Low

REF

14.318MHz

Low

Float (Controled by Byte2[5:3])

Float

Normal

Iref:2

or Float

Iref:2

or Float

Renasas clock generator I

2C Serial Interface Operation

1. Write mode

1.1

Controller (host) sends a start bit.

1.2

Controller (host) sends the write address D2 (h).

1.3

Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).

1.4

Controller (host) sends a begin byte M.

1.5

Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).

1.6

Controller (host) sends a byte count N.

1.7

Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).

1.8

Controller (host) sends data from byte M to byte M+N–1.

1.9

Renasas clock generator will acknowledge each byte one at a time.

1.10 Controller (host) sends a stop bit.

Start bit

1 bit

1 bit 1 bit

1 bit

7 bits

8 bits

Byte M

Slave

address

Begin Byte = M

Byte Count = N

R/W

D2(h)

Ack

1 bit

Ack

1 bit

Ack

Byte M+1

8 bits

1 bit

Stop bit

8 bits

Byte M+N–1

Ack

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