STV0042A datasheet(4/24 Pages) STMICROELECTRONICS

4 / 24 page

U75 L, U75 R

External deemphasis networks for channels left and

right. For each channel a capacitor and resistor in

parallel of 75

µs time constant are connectedbetween

hereandVREF to provide 75

µs de-emphasis.Internally

selectable is an internal resistor that can be pro-

grammedtobe addedin paralleltherebyconvertingthe

networkto approx50

µsde-emphasis(seecontrolblock

map).The value of theinternal resistors is 30k

Ω±30%.

Theamplifier forthisfilterisvoltageinput,currentoutput;

with

±500mVinputthe outputwill be ±55µA.

VOL L, VOL R

Themainaudiooutputfrom thevolumecontrolamplifier

the signal to get output signals as high as 2VRMS

(+12dB) on a DC bias of 4.8V.Control is from +12dBto

-26.75dB plus Mute with 1.25dB steps. This amplifier

has short circuit protection and is intended to drive a

SCART connector directly via AC coupling and meets

thestandardSCARTdriverequirements.Theseoutputs

featurehigh impedancemode for parallel connection.

S2 OUT L, S2 OUT R

These audio outputs are sourced directly from the

audioMUX, andas a result do not includeany volume

controlfunction.Theywill outputa1VRMS signalbiased

at4.8V.They are shortcircuit protected.Theseoutputs

feature high impedance mode for parallel connection

and meetSCART drive requirement.

S2 RTN L, S2 RTN R

These pins allow auxiliary audio signals to be con-

nected to the audio processor and hence makes

use of the on-chip volume control. For additional

details please refer to the audio switching table.

3 - Video Processing

B-BAND IN

AC-coupled video input from a tuner.

ZIN >10k

Ω ±25%. This drives an on-chipvideo ampli-

fier.TheotherinputofthisampisACgroundedbybeing

connectedto an internal VREF. The videoamplifierhas

selectablegain from 0dBto 12.7dBin 63 stepsand its

output signal can be selected normal or inverted.

UNCL DEEM

Deemphasized still unclamped output. It is also an

input of the video matrix.

VIDEEM1

Connected to an external de-emphasis network

(for instance 625 lines PAL de-emphasis).

VIDEEM2 / 22kHz

Connected to an external de-emphasis network

(for instance 525 lines NTSC or other video de-em-

phasis). Alternatively a precise 22kHz tone may be

output by I

2C bus control.

CLAMP IN

This pin clampsthemost negativeextremeof theinput

(the sync tips) to 2.7VDC (or appropriatevoltage). The

video at the clamp input is only 1VPP. This clamped

video which is de-emphasised, filtered and clamped

(energydispersalremoved) is normal, negativesyncs,

video. This signal drives the Video Matrix input called

Normal Video. It has a weak (1.0

µA ±15 %) stable

current source pulling the input towards GND. Other-

wise the input impedance is very high at DC to 1kHz

ZIN >2M

Ω. Video bandwidth through this is -1dB at

5.5MHz. The CLAMP input DC restore voltageis then

usedas a means for gettingthecorrect DC voltageon

the SCART outputs.

S2 VID RTN

External video input 1.0VPP AC coupled 75

Ω

source impedance. This input has a DC restoration

clamp on its input. The clamp sink current is 1

µA

±15% with the buffer ZIN >1MΩ. This signal is an

input to the Video Matrix.

S1 VID OUT, S2 VID OUT

Videodrivers for SCART 1 and SCART 2. An external

emitter follower bufferis required to drive a 150

Ω load.

The average DC voltage to be 1.5V on the O/P. The

signalis video2.0VPP 5.5MHzBW with synctip = 1.2V.

These pins get signals from the Video Matrix. The

signalselected from theVideo Matrix for outputon this

pin is controlled by a control register. This output also

featureahighimpedancemodeforparallelconnection.

V 12V

+12V double bonded : ESD+guard rings and video

circuit power.

V GND

Doubled bonded. Clean VID IN GND. Strategically

placed video power ground connection to reduce

video currents getting into the rest of the circuit.

4 - Control Block

GND 5V

The main power ground connection for the control

logic, registers, the I

2C bus interface, synthesizer

& watchdog and XTLOSC.

VDD 5V

Digital +5V power supply.

SCL

This is the I

2C busclock line. Clock= DC to 100kHz.

Requires external pull up eg. 10k

Ω to 5V.

SDA

This is the I

2C bus data line. Requires external pull

up eg. 10k

Ω to 5V.

XTL

This pin allows for the on-chip oscillator to be either

used with a crystal to ground of 4MHz or 8MHz, or

to be driven by an external clock source. The

external source can be either 4MHz or 8MHz. A

programmablebit in the control block removes a

÷2

block when the 4MHz option is selected.

PIN DESCRIPTION (continued)

STV0042A

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