PIN LIST

Pin Number

Pin Name

Type

Pin Description

SIGNAL INPUTS

51, 52, 53, 54, 55, 56

I [5..0]

I

In Phase Component, at twice the symbol frequency (2Fs).

57, 58, 59, 60, 61, 62

Q [5..0]

I

In Quadrature Component, at twice the symbol frequency (2Fs).

48

M_CLK

I

Master Clock Input, 2Fs. Sampling Clock of the External A to D Converters.

FRONT END CONTROLS

46

CLKREC

O

1 Bit Control Signal for the External CLK VCO. It must be Low-pass Filtered.

44

AGC

O

1 Bit Control Signal for the External AGC. It must be Low-pass Filtered.

35

D60

O

M_CLK Divided by 60

SIGNAL OUTPUTS

26, 25, 24, 23,

22, 21, 20, 19

D [7..0]

O

Output Data

29

CK_OUT

O

Output Byte Clock

30

STR_OUT

O

Output Synchronization Byte Signal

33

D/P

O

Data/Parity Signal

34

ERROR

O

Output Error Signal. Set in Case of uncorrected Block.

I

39

SCL

I

Serial Clock

40

SDA

I/O

Serial Data Bus

OTHER

47

MODE

I

0 = Mode A, 1 = Mode B

1, 2, 5, 6, 13, 14, 15,

16, 17, 18, 63, 64

TEST

O

Reserved for Manufacturing Test. It must remain unconnected

3, 7, 9, 11, 28, 32,

37, 41, 42, 49

I

Ground References

4, 8, 10, 12, 27,

31, 38, 43, 45, 50

I

3.3V Supply

36

NRES

I

Negative Reset

VITERBI DECODER

DEINTERLEAVER

REED SOLOMON DECODER

ENERGY DESCRAMBLER

NYQUIST

FILTER

DEROTATOR

AGC

LOCK

INDICATOR

DCO

TIMING

RECOVERY

CARRIER

OFFSET

MEASURE

CARRIER PHASE

TRACKING LOOP

DIVIDE BY 60

INTERFACE

AGC

D/P

ERROR

STR_OUT

CK_OUT

I[5...0]

Q[5...0]

CLKREC

D60

M_CLK

SCL

SDA

MODE

V

DD

V

SS

D[7..0]

STV0196B

C/N

INDICATOR

BLOCK DIAGRAM

STV0196B

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