STV0299B datasheet(7/36 Pages) STMICROELECTRONICS

7 / 36 page

STV0299B

7/36

FUNCTIONAL DESCRIPTION

The STV0299B is a multistandard demodulator

and error correction decoder IC for the reception

of QPSK and BPSK modulated signals. It is

intended for use in digital satellite television

applications. The IC can accept two standards of

QPSK modulated signals (DVB and DSS) as well

as BPSK modulated signals over a wide symbol

frequency range (from 1 to 50 Msymbols/s). The

signals are digitized via an integrated dual 6-bit

analog to digital converter, and interpolated and

digitally filtered by a Nyquist root filter (with a

settable roll-off value of either 0.35 or 0.20).

There are two built-in digital Automatic Gain

Controls (AGCs). The first AGC allows the tuner

gain to be controlled by the pulse density

modulated output. The second AGC performs

power optimization of the digital signal bandwidth

(internal to the STV0299B). The digital signal then

passes through the digital carrier loop fitted with

an on-chip derotator and tracking loop, lock

detector, and digital timing recovery.

Forward error correction is integrated by way of an

inner

Viterbi

soft

decoder,

and

outer

Reed-Solomon decoder.

4.1 Front End Interfaces

4.1.1

I2C Interface

The standard I2C protocol is used whereby the

first byte is Hex D0 for a write operation, or Hex

D1 for a read operation. The I2C interface

operates differently depending on whether it is in

normal or standby mode.

4.1.2

Write Operation (Normal Mode)

The byte sequence is as follows:

1 The first byte gives the device address plus the

direction bit (R/W = 0).

2 The second byte contains the internal address

of the first register to be accessed.

3 The next byte is written in the internal register.

Following

bytes

(if

any)

are

written

successive internal registers.

4 The transfer lasts until stop conditions are

encountered.

5 The

STV0299B

acknowledges

every

byte

transfer.

4.1.3

Read Operation (Normal Mode)

The address of the first register to read is

programmed in a write operation without data, and

terminated by the stop condition. Then, another

start is followed by the device address and R/

W = 1. All following bytes are now data to be read

at successive positions starting from the initial

address. Figure 2 shows the I2C Normal Mode

Write and Read Registers.

4.1.4

I2C Interface in Standby Mode

Only three registers can be addressed while in

standby mode: RCR (address 01 Hex), MCR

(address 02 Hex) and ACR (address 03 Hex).

These three registers can be either read or written

to (refer to Figure 3).

Only one register may be read or written to per

sequence (no increment). While in standby mode,

the Serial Clock (SCL) frequency must be lower than

one tenth of the CLK_IN frequency (fCLK_IN / 10).

Figure 2:

I2C Read and Write Operations in Normal Mode

Figure 3:

I2C Read and Write Operations in Standby Mode

Write registers 0 to 3 with AA, BB, CC, DD

Read registers 2 and 3

Start

Device

Address,

Write D0

ACK

Address

ACK

Data

ACK

Data

ACK

Data

ACK

Data

ACK

Stop

Start

Device Address, Write D0

ACK

Stop

Start

Device Address,

Read D1

ACK

Data Read CC

ACK

Data Read DD

ACK

Stop

Write operation

Read operation

Start

Device Address, Write D0

ACK

Data

ACK

Stop

Start

Device Address

, Read D0

ACK

Stop

Start

Device Address,

Read D1

ACK

Reader Data

ACK (or no

ACK

)

Stop

Note: 1 ACK is not absolutely necessary after Data

STV0299B 数据表(PDF) 7 Page - STMicroelectronics

STV0299B 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载

链接网址

STV0299B 数据表(PDF) 7 Page - STMicroelectronics

STV0299B 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表 下载

链接网址

数据表下载