ADL5802

Preliminary Technical Data

REV. PrA | Page 4 of 8

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 2. Pin Function Descriptions

Pin No.

Mnemonic

Function

1,2,5,8,14,

17,18, 21

GND

Device Common (DC Ground).

3,4

OP1+, OP1-

Channel 1Mixer differential output terminals. Need to apply bias through pull-up choke inductors or center

tap of the IF transfomer.

6, 13, 24

VPOS

Positive Supply Voltage. 5.0V Nominal

7

ENBL

Device Enable. Pull low to enable the device, pull high to disable.

9, 10

LOIP, LOIN

Differential LO input terminals. Internally matched to 50

Ω. Must be ac-coupled.

12

VSET

High IP3 bias control. For high IP3 performance apply ~4V. Improved NF performance and lower supply

current can be set by applying ~2V – 3V to the VSET pin. A resistor can be connected to the supply to raise

the voltage while a resistor to GND will lower the voltage.

15, 16

OP2+, OP2-

Channel 2 Mixer differential output terminals. Need to apply bias through pull-up choke inductors or center

tap of the IF transfomer.

19. 20

RF2+, RF2-

Differential RF input terminals for channel 2. Internally matched to 50

Ω. Must be ac-coupled.

22, 23

RF1+, RF1-

Differential RF input terminals for channel 1. Internally matched to 50

Ω. Must be ac-coupled.