Preliminary Technical Data

ADL5802

REV. PrA | Page 7 of 8

EVALUATION BOARD SCHEMATIC

Figure 11. Evaluation Board Schematic.

Table 3. Eval Board Configuration

Components

Function

Default Conditions

C1, C4, C6, C7, C8, C9, C10,

C11, C17, C18, R10, R12,

R19, R20, R21

Power Supply Decoupling. Nominal supply decoupling consists a

0.01 μF capacitor to ground in parallel with 10pF capacitors to

ground positioned as close to the device as possible. Series resistors

are provided for enhanced supply decoupling using optional ferrite

chip inductors.

C6, C7, C8 = 10pF (size 0402)

C9, C10, C11 = 0.01 μF (size 0402)

C1, C4, C17, C18 = open (size 0402)

R10, R12, R19, R20, R21 = 0

Ω (size

0402)

C5, C12, C13, C14, T3, T5,

RF1, RF2

RF Channel 1 and Channel 2 Input Interfaces. Input channels are ac-

coupled through C5, C12, C13 and C14. T3 and T4 are 1:1 baluns

used to interface to the 50-

Ω differential inputs.

C5, C12, C13, C14 = 1nF (size 0402)

T3, T5 = ETC1-1-13 (M/A-Com)

C15, C16,

L1, L2, L3, L4,

R2, R3, R6, R7, R13, R14,

R15, R16, R20, R21,

T2, T4,

IF1, IF2

IF Channel 1 and Channel 2 Output Interfaces. The 200-

Ω open

collector IF output interfaces are biased through the center taps of

4:1 impedance transformers at T2 and T4. C15 and C16 provide local

bypassing with R20 and R21 available for additional supply

bypassing. L1, L2, L3, and L4 provide the options when pull-up

choke inductors are used to bias the open-collector outputs. R6, R7,

R13, R14, R15, and R16 are provided for IF filtering and matching

options.

C15, C16 = 100pF (size 0402)

L1, L2, L3, L4 = open (size 0805)

R2, R3, R13, R14, R15, R16, R20, R21 =

0

Ω (size 0402)

R6, R7 = open (size 0402)

T2, T4 = TC4-1W+ (MiniCircuits)

C2, C3, R4, R5, T1, LO

LO Interface. C2 and C3 provide ac-coupling for the local oscillator

input. T1 is a 1:1 balun to allow single-ended interfacing to the

differential 50-

Ω local oscillator input. R4 and R5 provide the options

when differential LO interfaces are needed.

C2, C3 = 1nF (size 0402)

R4, R5 = 0

Ω (size 0402)

T1 = ETC1-1-13 (M/A-Com)

R1, R9, R11, ENBL1

ENABLE Interface. The ADL5802 can be disabled using the 3-pin

ENBL1 header. The ENBL pin is pulled up to VPOS through R9. R1 is

provided as an optional termination for the high impendace enable

interface.

R9 = 10k

Ω (size 0402)

R11 = 0

Ω (size 0402)

R1 = open (size 0402)

ENBL1 = 3-pin header and shunt

R22, R23, VSET

VSET Bias Control. R22 and R23 form an optional resistor divider

network between VPOS and GND, allowing for a fixed bias setting.

The default values are set up for 3.8 V at the VSET pin.

R22 = 866

Ω (size 0402)

R23 = 10k

Ω (size 0402)