FUNCTIONAL DESCRIPTION (continued)

VI - User Definable Character

The STV9420/21 allows the user to dynamically

define character(s) for his own needs (for a special

LOGO for example). Like the ROM characters, a

UDC is made of a 12 pixels x 18 slices dot matrix,

but one more slice is added for the vertical shad-

owing when several UDCs are gathered to make a

special great character (see Figure 8).

In a UDC, each pixel is defined with a bit, 1 refers

to foreground, and 0 to background color. Each

slice of a UDC uses 2 bytes :

add + 1

----

PX11 PX10 PX9 PX8

add

(even)

PX7 PX6 PX5 PX4 PX3

PX2 PX1 PX0

PX11 is the left most pixel. Character slice address :

SLICE ADDRESS = 38 x (CHARACTER NUMBER)

+ (SLICE NUMBER).

Where :

- CHARACTER NUMBER is the number given by

the character code,

- SLICE NUMBER is the number given by the slice

interpolator (n

° of the current slice of the strip :

1 < <18)

VII - ROM Character Generator

The STV9420/21 includes a ROM character gen-

erator which is made of 128 alphanumeric or

graphic characters (see Table 1)

VIII - PLL

The PLL function of the STV9420/21 provides the

internal pixel clock locked on the horizontal synchro

signal and used by the display processor to gener-

ate the R, G, B and fast blanckingsignals. It is made

of 2 PLLs. The first one analogic (see Figure 9),

provides a high frequency signal locked on the

crystal frequency. The frequency multiplier is given

by :

N= 2

⋅ (FM[3:0] + 3)

Where FM[3:0] is the value of the FREQUENCY

MULTIPLIER register.

FILTRE

%N

VCO

Figure 9 : Analogic PLL

ALGO

%M

%D

err(n)

D(n)

Figure 10 : Digital PLL

The second PLL, full digital (see Figure 10), pro-

vides a pixel frequency locked on the horizontal

synchro signal. The ratio between the frequencies

of these 2 signals is :M = 12 x (LD[5:0] + 1)

Where LD[5:0] is the value of the LINE DURATION

register.

VIII.1 - Programming of the PLL Registers

Frequency Multiplier (@3FF7)

This register gives the ratio between the crystal

frequency and the high frequency of the signal

used by the 2

clock. The value of this high frequency must be

near to 200MHz (for example if the crystal is a

8MHz, the value of FM must be equal to 10) and

greater than 6 x (pixel frequency).

Initial Pixel Period (@3FF6)

This register allows to increase the speed of the

convergence of the PLL when the horizontal fre-

quency changes (new graphic standart). The rela-

PP[7:0]

= round







8

⋅

2

12

± 24







Locking Condition Time Constant (@ 3FF4)

This register gives the constants AS[2:0] and

BS[2:0] used by the algo part of the PLL (see Figure

10) to calculate, from the phase error, err(n), the

new value, D(n), of the division of the high fre-

quency signal to provide the pixel clock. These two

constants are used only in locking condition, which

is true, if the phase error is less than a fixed value

during at least, 4 scan lines. If The phase error

becomes greater than the fixed value, the PLL is

not in locking condition but in capture process. In

this case, the algo part of the PLL used the other

constants, AF[2:0] and BF[2:0], given by the next

register.

Capture Process Time Constant (@ 3FF5)

The choice between these two time constants

(locking condition or capture process) allows to

decrease the capture process time by changing the

time response of the PLL.

STV9420 - STV9421

12/16