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M35062 数据表(PDF) 5 Page - Renesas Technology Corp |
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M35062 数据表(HTML) 5 Page - Renesas Technology Corp |
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5 / 41 page  4 MITSUBISHI MICROCOMPUTERS M35062-XXXSP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS : Name or value changes by definite ratio. : The same name or value continues. MEMORY CONSTRUCTION Address 00016 to 2A716 are assigned to the display RAM, 2A816 to 2B016 are assigned to the display control registers and 30016 to 36C16 are assigned to SYRAM. The internal circuit is reset and all display control registers (address 2A816 to 2B016) are set to “0”. The memory constitution of display RAM and register is shown in Figure 1 and the memory constitution of SYRAM is shown in Figure 2. add- ress 00016 2A716 2A816 2A916 2AA16 2AB16 2AC16 2AD16 2AE16 2AF16 2B016 DA17 SB SB – – – – – – – PC7 – DA16 SG SG TEST 3 – – – – TEST 23 – PC6 TEST 19 DA15 SR SR TEST 2 – – TEST 26 – TEST 22 – PC5 TEST 18 DA14 0 0 0 TEST 1 BLINK 3 TEST 12 TEST 25 LBLACK SERS 0 – PC4 TEST 17 DA13 0 0 0 TEST 0 BLINK 2 EQP PHASE 2 LINE B – – PC3 TEST 24 DA12 0 0 0 TEST 11 BLINK 1 TEST 20 PHASE 1 LINE G – SEND 4 PC2 LEVEL 2 DA10 SYC1 SYC1 HP8 HSZ 16 VSZ 16 DSP0 16 DSP1 16 ERS 16 SEND 2 PC0 LEVEL 0 DAF SYC0 SYC0 HP7 HSZ 15 VSZ 15 DSP0 15 DSP1 15 ERS 15 SEND 1 ALL24 __ INT NON DAE BB BB HP6 HSZ 14 VSZ 14 DSP0 14 DSP1 14 ERS 14 SEND 0 SRAND 2 PAL ___ NTSC DAD BG BG HP5 HSZ 13 VSZ 13 DSP0 13 DSP1 13 ERS 13 SST 4 SRAND 1 MPAL DAC BR BR HP4 HSZ 12 VSZ 12 DSP0 12 DSP1 12 ERS 12 SST 3 SRAND 0 PALH DAB BLINK BLINK BLINK HP3 HSZ 11 VSZ 11 DSP0 11 DSP1 11 ERS 11 SST 2 PTD 5 TEST 16 DAA CB CB HP2 HSZ 10 VSZ 10 DSP0 10 DSP1 10 ERS 10 SST 1 PTD 4 TEST 15 DA9 CG CG HP1 HSZ 9 VSZ 9 DSP0 09 DSP1 09 ERS 9 SST 0 PTD 3 SEPV1 DA8 CR CR HP0 HSZ 8 VSZ 8 DSP0 08 DSP1 08 ERS 8 SLIN 4 PTD 2 SEPV0 DA7 0 0 0 VP7 HSZ 7 VSZ 7 DSP0 07 DSP1 07 ERS 7 SLIN 3 PTD 1 BLK DA6 C6 C6 VP6 HSZ 6 VSZ 6 DSP0 06 DSP1 06 ERS 6 SLIN 2 PTD 0 – DA5 C5 C5 VP5 HSZ 5 VSZ 5 DSP0 05 DSP1 05 ERS 5 SLIN 1 PTC 5 DSP ONV DA4 C4 C4 VP4 HSZ 4 VSZ 4 DSP0 04 DSP1 04 ERS 4 SLIN 0 PTC 4 DSP ON DA3 C3 C3 VP3 HSZ 3 VSZ 3 DSP0 03 DSP1 03 ERS 3 SBIT 3 PTC 3 – DA2 C2 C2 VP2 HSZ 2 VSZ 2 DSP0 02 DSP1 02 ERS 2 SBIT 2 PTC 2 SEL COR DA0 C0 C0 VP0 HSZ 0 VSZ 0 DSP0 00 DSP1 00 ERS 0 SBIT 0 PTC 0 EX SY color setting DA11 SYC2 SYC2 TEST 10 BLINK 0 HIDE PHASE 0 LINE R – SEND 3 PC1 LEVEL 1 Raster color setting Character color setting Character setting Table 1 The memory constitution of display RAM and register Table 2 The memory constitution of SYRAM add- ress 30016 30C16 31016 31C16 35016 35C16 36016 36C16 0 0 DA17 to DAD 0 0 DAC SYEX SYEX SYEX SYEX SYEX SYEX SYEX SYEX DAB S00B S00B S01B S01B S05B S05B S06B S06B DAA S00A S00A S01A S01A S05A S05A S06A S06A DA9 S009 S009 S019 S019 S059 S059 S069 S069 DA8 S008 S008 S018 S018 S058 S058 S068 S068 DA7 S007 S007 S017 S017 S057 S057 S067 S067 DA6 S006 S006 S016 S016 S056 S056 S066 S066 DA5 S005 S005 S015 S015 S055 S055 S065 S065 DA4 S004 S004 S014 S014 S054 S054 S064 S064 DA3 S003 S003 S013 S013 S053 S053 S063 S063 DA2 S002 S002 S012 S012 S052 S052 S062 S062 DA1 S001 S001 S011 S011 S051 S051 S061 S061 DA0 S000 S000 S010 S010 S050 S050 S060 S060 SYRAM code 0016 0116 0516 0616 TESTn (n = number) is MITSUBISHI test memory. Set 0 to all bits. SYRAM setting DA1 C1 C1 VP1 HSZ 1 VSZ 1 DSP0 01 DSP1 01 ERS 1 SBIT 1 PTC 1 SCOR |
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