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M35062 数据表(PDF) 30 Page - Renesas Technology Corp |
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M35062 数据表(HTML) 30 Page - Renesas Technology Corp |
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30 / 41 page  MITSUBISHI MICROCOMPUTERS M35062-XXXSP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 29 (2) To switch from external sync to internal sync when the oscillator is already stable (a) Set the registers DIPON and DISPONV = low. (The display is turned off.) (b) Disable data input during a 20 ms wait state (internal oscillator stabilization period). (c) Set the registers EX and PAL/NTSC = high and INT/NON = low. (The display is temporarily placed in the interlaced mode.) (d) Disable data input during a 30 ms wait state (internal oscillator stabilization period). (e) Set the registers INT/NON and PALH = high (for 628 scanning lines). (The scanning fields are fixed to the first field.) (f) Set up other registers, SYRAM, and display RAM. (g) Set the registers DIPON and DISPONV = high. (The display is turned on.) 10. Notes on fsc signal input (1) This IC amplifies the subcarrier frequency (fsc) signal (NTSC sys- tem: 3.580 MHz, PAL system: 4.434 MHz, M-PAL system: 3.576 MHz) input to the OSCIN pin and generates the composite video signal internally. The amplified fsc signal can be destabilized in the following cases. (a) When the fsc signal is outside of recommended operating conditions (b) When the waveform of the fsc signal is distorted (c) When DC level in the fsc waveform fluctuates When the amplified signal is unstable, the composite video signal generated inside the IC is also unstable in terms of synchroniza- tion with the subcarrier and phase. Consequently, this results in color flicker and lost synchronization when the composite video signal is generated. Make note of the fact that this may prevent a stable blue background from being formed. (2) When switching to internal synchronization from external syn- chronization (fsc signal is OFF), start fsc signal input 20 m sec or more before the internal oscillator circuit stabilizes. 11. Procedure for fixing to the first field in PAL system The M35062-XXXSP allows to fix the scanning fields to the first field during PAL system noninterlaced display (internally synchronized). In this case, the display must be placed in the interlaced mode tem- porarily before entering the noninterlaced mode in order to ensure that the scanning fields are fixed. Follow the setup procedure de- scribed below. (1) When powering on (a) Turn on the power (AC pin = low). (b) Deactivate auto clear (AC pin = high). (c) Disable data input during a 200 ms wait state (internal stabili- zation period). (d) Set the registers LEVEL 0 and 2 = high and LEVEL 1 = low. (e) Disable data input during a 20 ms wait state (internal oscilla- tor stabilization period). (f) Set the registers EX and PAL /NTSC = high and INT/NON = low. (The display is temporarily placed in the interlaced mode.) (g) Disable data input during a 30 ms wait state (internal oscilla- tor stabilization period). (h) Set the registers INT/NON and PALH = high (for 628 scanning lines). (The scanning fields are fixed to the first field.) (i) Set up the register PCn. (j) Disable data input during a 20 ms wait state (internal oscilla- tor stabilization period). (k) Set up other registers. (l) Set up SYRAM. (m) Set up the display RAM. (n) Set the registers DIPON and DISPONV = high.(The display is turned on.) |
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