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SH7261 数据表(PDF) 73 Page - Renesas Technology Corp

部件名 SH7261
功能描述  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SH7261 数据表(HTML) 73 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 41 of 1312
REJ09B0320-0200
Instruction Formats
Source
Operand
Destination
Operand
Example
ni format
nnnn
iiii
xxxx
15
0
iiii
iiiiiiii: Immediate
nnnn: Register
direct
ADD
#imm,Rn
nnnn: Register
direct
iii: Immediate
—
BLD
#imm3,Rn
ni3 format
xxxx
nnnn
xxxx
15
0
iii
x
—
nnnn: Register
direct
iii: Immediate
BST
#imm3,Rn
ni20 format
iiii
iiii
iiii
iiii
15
0
xxxx
iiii
xxxx
nnnn
32
16
iiiiiiiiiiiiiiiiiiii:
Immediate
nnnn: Register
direct
MOVI20
#imm20, Rn
nnnndddddddddddd
: Register indirect
with displacement
iii: Immediate
—
BLD.B
#imm3,@(disp12,Rn)
nid format
xiii
dddd
dddd
dddd
15
0
xxxx
nnnn
xxxx
xxxx
32
16
—
nnnndddddddddddd
: Register indirect
with displacement
iii: Immediate
BST.B
#imm3,@(disp12,Rn)
Note:
*
In multiply-and-accumulate instructions, nnnn is the source register.



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