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SH7261 数据表(PDF) 86 Page - Renesas Technology Corp |
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SH7261 数据表(HTML) 86 Page - Renesas Technology Corp |
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86 / 1348 page  Section 2 CPU Rev. 2.00 Sep. 07, 2007 Page 54 of 1312 REJ09B0320-0200 Compatibility Instruction Instruction Code Operation Execu- tion Cycles T Bit SH2, SH2E SH4 SH-2A EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended → Rn 1 Yes Yes Yes MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits 4 Yes Yes Yes MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits 3 Yes Yes Yes MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL 32 × 32 → 32 bits 2 Yes Yes Yes MULR R0,Rn 0100nnnn10000000 R0 × Rn → Rn 32 × 32 → 32 bits 2 Yes MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn × Rm → MACL 16 × 16 → 32 bits 1 Yes Yes Yes MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn × Rm → MACL 16 × 16 → 32 bits 1 Yes Yes Yes NEG Rm,Rn 0110nnnnmmmm1011 0-Rm → Rn 1 Yes Yes Yes NEGC Rm,Rn 0110nnnnmmmm1010 0-Rm-T → Rn, borrow → T 1 Borrow Yes Yes Yes SUB Rm,Rn 0011nnnnmmmm1000 Rn-Rm → Rn 1 Yes Yes Yes SUBC Rm,Rn 0011nnnnmmmm1010 Rn-Rm-T → Rn, borrow → T 1 Borrow Yes Yes Yes SUBV Rm,Rn 0011nnnnmmmm1011 Rn-Rm → Rn, underflow → T 1 Over- flow Yes Yes Yes |
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