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HD6432351 数据表(PDF) 97 Page - Renesas Technology Corp |
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HD6432351 数据表(HTML) 97 Page - Renesas Technology Corp |
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97 / 1025 page ![]() Section 2 CPU Rev. 3.00 Sep 15, 2006 page 63 of 988 REJ09B0330-0300 (c) Interrupt control mode 0 (d) Interrupt control mode 2 CCR PC (24 bits) SP Note: * Ignored when returning. CCR PC (24 bits) SP EXR Reserved* (a) Interrupt control mode 0 (b) Interrupt control mode 2 CCR CCR* PC (16 bits) SP CCR CCR* PC (16 bits) SP EXR Reserved* Normal mode Advanced mode Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. |
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