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H8S/2240 数据表(PDF) 400 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 400 Page - Renesas Technology Corp |
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400 / 818 page ![]() Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 358 of 772 REJ09B0355-0300 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.50 shows the timing in this case. Input capture signal Write signal Address φ TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 9.50 Contention between TGR Write and Input Capture |
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