H8SSLASH2240 datasheet(403/818 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 361 of 772

REJ09B0355-0300

Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and

overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is

not set.

Figure 9.53 shows the operation timing in the case of contention between a TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

H'FFFF

Prohibited

TCNT write data

TCFV flag

Figure 9.53 Contention between TCNT Write and Overflow

Multiplexing of I/O Pins

In the H8S/2245 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the

TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and

the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match

output should not be performed from a multiplexed pin.

Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source or DTC activation source. Interrupts should therefore be disabled

before entering module stop mode.

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