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H8S/2240 数据表(PDF) 401 Page - Renesas Technology Corp

部件名 H8S/2240
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2240 数据表(HTML) 401 Page - Renesas Technology Corp

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Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.3.00 Mar. 26, 2007 Page 359 of 772
REJ09B0355-0300
Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation
takes precedence and the write to the buffer register is not performed.
Figure 9.51 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T1
T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 9.51 Contention between Buffer Register Write and Input Capture



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