H8SSLASH2240 datasheet(147/818 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.3.00 Mar. 26, 2007 Page 105 of 772

REJ09B0355-0300

5.1.3

Pin Configuration

Table 5.1 summarizes the pins of the interrupt controller.

Table 5.1

Interrupt Controller Pins

Name

Symbol

I/O

Function

Nonmaskable interrupt

NMI

Input

Nonmaskable external interrupt; rising or

falling edge can be selected

External interrupt

requests 7 to 0

IRQ7 to IRQ0 Input

Maskable external interrupts; rising, falling, or

both edges, or level sensing, can be selected

5.1.4

Table 5.2 summarizes the registers of the interrupt controller.

Table 5.2

Interrupt Controller Registers

Name

Abbreviation

R/W

Initial Value

Address*

System control register

SYSCR

R/W

H'01

H'FF39

IRQ sense control register H

ISCRH

R/W

H'00

H'FF2C

IRQ sense control register L

ISCRL

R/W

H'00

H'FF2D

IRQ enable register

IER

R/W

H'00

H'FF2E

IRQ status register

ISR

R/(W)*

H'00

H'FF2F

Interrupt control register A

ICRA

R/W

H'00

H'FEC0

Interrupt control register B

ICRB

R/W

H'00

H'FEC1

Interrupt control register C

ICRC

R/W

H'00

H'FEC2

Notes: 1. Lower 16 bits of the address.

2. Can only be written with 0 for flag clearing.

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