H8SSLASH2240 datasheet(151/818 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.3.00 Mar. 26, 2007 Page 109 of 772

REJ09B0355-0300

The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or

both edge detection, or level sensing, for the input at pins

IRQ7 to IRQ0.

The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.

Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and

B (IRQ0SCA, IRQ0SCB)

Bits 15 to 0

IRQ7SCB to

IRQ0SCB

IRQ7SCA to

IRQ0SCA

Description

Interrupt request generated at

IRQ7 to IRQ0 input low level

(initial value)

Interrupt request generated at falling edge of

IRQ7 to IRQ0 input

Interrupt request generated at rising edge of

IRQ7 to IRQ0 input

Interrupt request generated at both falling and rising edges of

IRQ7 to IRQ0 input

5.2.5

IRQ Status Register (ISR)

IRQ7F

R/(W)*

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

R/W

Note: * Only 0 can be written, to clear the flag.

ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt

requests.

ISR is initialized to H'00 by a reset and in hardware standby mode.

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