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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2240 数据表(PDF) 152 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 152 Page - Renesas Technology Corp |
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152 / 818 page  Section 5 Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 110 of 772 REJ09B0355-0300 Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF Description 0 [Clearing conditions] (Initial value) • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When IRQn interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high • When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) • When DTC is activated by IRQn interrupt while DISEL bit of MRB in DTC is 0. 1 [Setting conditions] • When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) • When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) • When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) • When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) Note: n = 7 to 0 |
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