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H8S/2240 数据表(PDF) 149 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 149 Page - Renesas Technology Corp |
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149 / 818 page  Section 5 Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 107 of 772 REJ09B0355-0300 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC) 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W 3 ICR3 0 R/W 0 ICR0 0 R/W 2 ICR2 0 R/W 1 ICR1 0 R/W Bit Initial value R/W : : : The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI. The correspondence between ICR settings and interrupt sources is shown in table 5.3. The ICR registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—Interrupt Control Level (ICRn): Bit n ICRn Description 0 The corresponding interrupt requests have priority level 0 (low priority) (Initial value) 1 The corresponding interrupt requests have priority level 1 (high priority) Note: n = 7 to 0 Table 5.3 Correspondence between Interrupt Sources and ICR Settings Bits Register 76 54 32 10 ICRA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTC Watchdog timer — ICRB — A/D converter TPU channel 0 TPU channel 1 TPU channel 2 —— — ICRC 8-bit timer channel 0 8-bit timer channel 1 — SCI channel 0 SCI channel 1 SCI channel 2 —— |
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