H8SSLASH2240 datasheet(213/818 Pages) RENESAS

部件名	H8S/2240

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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213 / 818 page

Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 171 of 772

REJ09B0355-0300

(3) Relationship between Chip Select (

CS) Signal and Read (RD

RD) Signal

Depending on the system's load conditions, the

RD signal may lag behind the CS signal. An

example is shown in figure 6.22.

In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap

between the bus cycle A

RD signal and the bus cycle B CS signal.

Setting idle cycle insertion, as in (b), however, will prevent any overlap between the

RD and CS

signals.

In the initial state after reset release, idle cycle insertion (b) is set.

Address bus

Bus cycle A

Bus cycle B

Possibility of overlap between

CS (area B) and RD

Address bus

Bus cycle A

Bus cycle B

CS (area A)

CS (area B)

CS (area A)

CS (area B)

(a) Idle cycle not inserted

(ICIS1 = 0)

(b) Idle cycle inserted

(Initial value ICIS1 = 1)

Figure 6.22 Relationship between Chip Select (

CS) and Read (RD

RD)

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