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H8S/2240 数据表(PDF) 216 Page - Renesas Technology Corp

部件名 H8S/2240
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2240 数据表(HTML) 216 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 174 of 772
REJ09B0355-0300
6.8.4
Transition Timing
Figure 6.23 shows the timing for transition to the bus-released state.
CPU
cycle
External bus released state
CPU cycle
Address
Minimum
1 state
T0
T1
T2
φ
Address bus
Data bus
AS
HWR, LWR
BREQ
BACK
High impedance
[1]
[2]
[3]
[4]
[5]
[1]
Low level of
BREQ pin is sampled at rise of T
2 state.
[2]
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.
[3]
BREQ pin state is still sampled in external bus released state.
[4]
High level of
BREQ pin is sampled.
[5]
BACK pin is driven high, ending bus release cycle.
High impedance
High impedance
High impedance
RD
High impedance
Figure 6.23 Bus-Released State Transition Timing



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