H8SSLASH2240 datasheet(227/818 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 185 of 772

REJ09B0355-0300

7.2.7

DTC Enable Registers (DTCER)

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

R/W

The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF,

with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or

disable DTC service for the corresponding interrupt sources.

The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.

Bit n—DTC Activation Enable (DTCEn)

Bit n

DTCEn

Description

DTC activation by this interrupt is disabled

(Initial value)

[Clearing conditions]

1. When DISEL = 1 and data transfer ends

2. When the specified number of transfers end

DTC activation by this interrupt is enabled

[Holding condition]

When DISEL = 0 and the specified number of transfers have not ended

Note:

n = 7 to 0

A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence

between interrupt sources and DTCE bits is shown in table 7.3, together with the vector number

generated for each interrupt controller.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are masked, multiple activation sources can be set at one time by writing data after executing a

dummy read on the relevant register.

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