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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2240 数据表(PDF) 230 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 230 Page - Renesas Technology Corp |
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230 / 818 page  Section 7 Data Transfer Controller Rev.3.00 Mar. 26, 2007 Page 188 of 772 REJ09B0355-0300 Figure 7.2 shows a flowchart of DTC operation. Start Next transfer Read DTC vector Read register information Data transfer Write register information Clear an activation flag Note: * For details on interrupt handling, see the sections dealing with the individual peripheral modules. CHNE = 1? Transfer counter = 0 or DISEL = 1? No No Yes Yes Clear DTCER Interrupt exception handling End * Figure 7.2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. |
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