H8SXSLASH1663 datasheet(599/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 547 of 1102

REJ09B0294-0100

(2) Examples of Buffer Operation

(a) When TGR is an output compare register

Figure 10.15 shows an operation example in which PWM mode 1 has been designated for channel

0, and buffer operation has been designated for TGRA and TGRC. The settings used in this

example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at

compare match B.

As buffer operation has been set, when compare match A occurs, the output changes and the value

in buffer register TGRC is simultaneously transferred to timer general register TGRA. This

operation is repeated each time compare match A occurs.

For details on PWM modes, see section 10.4.5, PWM Modes.

TCNT value

TGRB_0

H'0000

TGRC_0

TGRA_0

H'0200

H'0520

TIOCA

H'0200

H'0450

H'0520

H'0450

TGRA_0

H'0450

H'0200

Transfer

Time

Figure 10.15 Example of Buffer Operation (1)

H8SX/1663 数据表(PDF) 599 Page - Renesas Technology Corp