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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663 数据表(PDF) 602 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 602 Page - Renesas Technology Corp |
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602 / 1158 page  Section 10 16-Bit Timer Pulse Unit (TPU) Rev.1.00 Jun. 07, 2006 Page 550 of 1102 REJ09B0294-0100 (2) Examples of Cascaded Operation Figure 10.18 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_2 clock TCNT_2 H'FFFF H'0000 H'0001 TIOCA1, TIOCA2 TGRA_1 H'03A2 TGRA_2 H'0000 TCNT_1 clock TCNT_1 H'03A1 H'03A2 Figure 10.18 Example of Cascaded Operation (1) Figure 10.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCNT_2 FFFD TCNT_1 0001 TCLKD FFFE FFFF 0000 0001 0002 0001 0000 FFFF 0000 0000 Figure 10.19 Example of Cascaded Operation (2) |
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