H8SXSLASH1663 datasheet(726/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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726 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 674 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

FER

R/(W)* Framing Error

Indicates that a framing error has occurred during

reception in asynchronous mode and the reception ends

abnormally.

[Setting condition]

• When the stop bit is 0

In 2-stop-bit mode, only the first stop bit is checked

whether it is 1 but the second stop bit is not checked.

Note that receive data when the framing error occurs

is transferred to RDR, however, the RDRF flag is not

set. In addition, when the FER flag is being set to 1,

the subsequent serial reception cannot be performed.

In clocked synchronous mode, serial transmission

also cannot continue.

[Clearing condition]

• When 0 is written to FER after reading FER = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

Even when the RE bit in SCR is cleared, the FER flag

is not affected and retains its previous value.

H8SX/1663 数据表(PDF) 726 Page - Renesas Technology Corp