H8SXSLASH1663 datasheet(728/1158 Pages) RENESAS

728 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 676 of 1102

REJ09B0294-0100

Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/(W)* Transmit Data Register Empty

Indicates whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• When a TXI interrupt request is issued allowing

DMAC or DTC to write data to TDR

RDRF

R/(W)* Receive Data Register Full

Indicates whether receive data is stored in RDR.

[Setting condition]

• When serial reception ends normally and receive data

is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• When an RXI interrupt request is issued allowing

DMAC or DTC to read data from RDR

The RDRF flag is not affected and retains its previous

value even when the RE bit in SCR is cleared to 0.

Note that when the next reception is completed while the

RDRF flag is being set to 1, an overrun error occurs and

the received data is lost.

H8SX/1663 数据表(PDF) 728 Page - Renesas Technology Corp

H8SX/1663 数据表(HTML) 728 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载