H8SXSLASH1663 datasheet(731/1158 Pages) RENESAS

731 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 679 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

TEND

Transmit End

This bit is set to 1 when no error signal is sent from the

receiving side and the next transmit data is ready to be

transferred to TDR.

[Setting conditions]

• When both the TE and ERS bits in SCR are 0

• When ERS = 0 and TDRE = 1 after a specified time

passed after completion of 1-byte data transfer. The

set timing depends on the register setting as follows:

When GM = 0 and BLK = 0, 2.5 etu after transmission

start

When GM = 0 and BLK = 1, 1.5 etu after transmission

start

When GM = 1 and BLK = 0, 1.0 etu after transmission

start

When GM = 1 and BLK = 1, 1.0 etu after transmission

start

[Clearing conditions]

• When 0 is written to TEND after reading TEND = 1

• When a TXI interrupt request is issued allowing

DMAC or DTC to write the next data to TDR

MPB

Multiprocessor Bit

Not used in smart card interface mode.

MPBT

R/W

Multiprocessor Bit Transfer

Write 0 to this bit in smart card interface mode.

Note:

Only 0 can be written, to clear the flag.

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