H8SXSLASH1663 datasheet(733/1158 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 681 of 1102

REJ09B0294-0100

15.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control

independently for each channel, different bit rates can be set for each channel. Table 15.2 shows

the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and

clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and

it can be read from or written to by the CPU at all times.

Table 15.3

Relationships between N Setting in BRR and Bit Rate B

Mode

ABCS Bit Bit Rate

Error

B =

− 1

64 × 2

× B

2n – 1

φ × 106

Error (%) = {

– 1 } × 100

B × 64 × 2

× (N + 1)

2n – 1

φ × 106

Asynchronous

mode

B =

− 1

32 × 2

× B

2n – 1

φ × 106

Error (%) = {

– 1 } × 100

B × 32 × 2

× (N + 1)

2n – 1

φ × 106

Clocked synchronous mode

N =

− 1

8 × 2

× B

2n – 1

φ × 106

Smart card interface mode

N =

− 1

S × 2

× B

φ × 106

2n + 1

Error (%) =

B × S × 2

× (N + 1)

– 1 × 100

2n + 1

φ × 106

{

}

[Legend]

Bit rate (bit/s)

BRR setting for baud rate generator (0

≤ N ≤ 255)

φ:

Operating frequency (MHz)

n and S: Determined by the SMR settings shown in the following table.

SMR Setting

CKS1

CKS0

BCP1

BCP0

372

256

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