H8SXSLASH1663 datasheet(768/1158 Pages) RENESAS

768 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 716 of 1102

REJ09B0294-0100

15.6.2

SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)

Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize

the SCI as described in a sample flowchart in figure 15.18. When the operating mode, transfer

format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When

the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not

initialize the RDRF, PER, FER, and ORER flags, or RDR.

Wait

Start initialization

Set data transfer format in

SMR and SCMR

Yes

Set value in BRR

Set corresponding bit in ICR to 1

[2]

[3]

Set TE or RE bit in SCR to 1, and

set RIE, TIE, TEIE, and MPIE bits

[5]

1-bit interval elapsed?

Set CKE1 and CKE0 bits in SCR

(TE and RE bits are 0)

[1]

Set the bit in ICR for the corresponding

pin when receiving data or using an

external clock.

[2] Set the clock selection in SCR. Be sure

to clear bits RIE, TIE, TEIE, and MPIE,

and bits TE and RE, to 0.

[3] Set the data transfer format in SMR and

SCMR.

[4] Write a value corresponding to the bit

rate to BRR. This step is not necessary

if an external clock is used.

[5] Wait at least one bit interval, then set

the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE TEIE, and MPIE

bits. Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Note: In simultaneous transmit and receive operations, the TE and RE bits should both

be cleared to 0 or set to 1 simultaneously.

Clear TE and RE bits in SCR to 0

[4]

Figure 15.18 Sample SCI Initialization Flowchart

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