H8SXSLASH1663 datasheet(790/1158 Pages) RENESAS

790 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 738 of 1102

REJ09B0294-0100

Data transmission/reception using the DTC or DMAC is also possible in smart card interface

mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are

simultaneously set to 1, thus generating a TXI interrupt. This activates the DTC or DMAC by a

TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of

DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0

at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically re-transmits the

same data. During re-transmission, the TEND flag remains as 0, thus not activating the DTC or

DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of

bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR,

which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by

previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at

error occurrence.

When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or

DMAC prior to making SCI settings. For DTC or DMAC settings, see section 8, Data Transfer

Controller (DTC) and section 7, DMA Controller (DMAC).

In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This

activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI

request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is

automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the RDRF

flag is not set but the error flag is set. Therefore, the DTC or DMAC is not activated and an ERI

interrupt request is issued to the CPU instead; the error flag must be cleared.

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