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H8SX/1663 数据表(PDF) 788 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 788 Page - Renesas Technology Corp

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Section 15 Serial Communication Interface (SCI, IrDA, CRC)
Rev.1.00 Jun. 07, 2006 Page 736 of 1102
REJ09B0294-0100
15.9
Interrupt Sources
15.9.1
Interrupts in Normal Serial Communication Interface Mode
Table 15.14 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the
DTC or DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer
by the DTC or DMAC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC or DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at
data transfer by the DTC or DMAC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by
the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine
later.
Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and
the group of SCI_5 and SCI_6.
Table 15.14 SCI Interrupt Sources (SCI_0, 1, 2, and 4)
Name
Interrupt Source
Interrupt Flag
DTC Activation
DMAC Activation
Priority
ERI
Receive error
ORER, FER, or PER
Not possible
Not possible
High
RXI
Receive data full
RDRF
Possible
Possible
TXI
Transmit data empty TDRE
Possible
Possible
TEI
Transmit end
TEND
Not possible
Not possible
Low



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