数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

H8SX/1663 数据表(PDF) 828 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 828 Page - Renesas Technology Corp

Back Button H8SX/1663 Datasheet HTML 824Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 825Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 826Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 827Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 828Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 829Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 830Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 831Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 832Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 828 / 1158 page
background image
Section 16 USB Function Module (USB)
Rev.1.00 Jun. 07, 2006 Page 776 of 1102
REJ09B0294-0100
16.3.23
Configuration Value Register (CVR)
This register stores the Configuration, Interface, or Alternate set value when the Set Configuration
or Set Interface command from the host is correctly received.
Bit
Bit Name
Initial Value
R/W
7
CNFV1
0
R
6
CNFV0
0
R
5
INTV1
0
R
4
INTV0
0
R
3
0
R
2
ALTV2
0
R
1
ALTV1
0
R
0
ALTV0
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
6
CNFV1
CNFV0
All 0
R
These bits store Configuration Setting value when
they receive Set Configuration command. CNFV is
updated when the SETC bit in IFR2 is set to 1.
5
4
INTV1
INTV0
All 0
R
These bits store Interface Setting value when they
receive Set Interface command. INTV is updated
when the SETI bit in IFR2 is set to 1.
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
ALTV2
0
R
1
ALTV1
0
R
0
ALTV0
0
R
These bits store Alternate Setting value when they
receive Set Interface command. ALTV2 to ALTV0 are
updated when the SETI bit in IFR2 is set to 1.
16.3.24
Control Register (CTLR)
This register sets functions for bits ASCE, PWMD, RSME, and, PWUPS.
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
RWUPS
0
R
3
RSME
0
R/W
2
PWMD
0
R/W
1
ASCE
0
R/W
0
0
R



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com