H8SXSLASH1663 datasheet(865/1158 Pages) RENESAS

865 / 1158 page

Section 16 USB Function Module (USB)

Rev.1.00 Jun. 07, 2006 Page 813 of 1102

REJ09B0294-0100

16.10

Usage Notes

16.10.1

Receiving Setup Data

Note the following for EPDR0s that receives 8-byte setup data:

1. As a latest setup command must be received in high priority, the write from the USB bus takes

priority over the read from the CPU. If the next setup command reception is started while the

CPU is reading data after the data is received, the read from the CPU is forcibly terminated.

Therefore, the data read after reception is started becomes invalid.

2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data

received at the next setup cannot be read correctly.

16.10.2

Clearing the FIFO

If a USB cable is disconnected during data transfer, the data being received or transmitted may

remain in the FIFO. When disconnecting a USB cable, clear the FIFO.

While a FIFO is transferring data, it must not be cleared.

16.10.3

Overreading and Overwriting the Data Registers

Note the following when reading or writing to a data register of this module.

(1) Receive data registers

The receive data registers must not be read exceeding the valid amount of receive data, that is, the

number of bytes indicated by the receive data size register. Even for EPDR1 which has double

FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the

current valid FIFO buffer, be sure to write 1 to EP1RDFN in TRG, which switches the valid

buffer, updates the receive data size to the new number of bytes, and enables the next data to be

received.

(2) Transmit data registers

The transmit data registers must not be written to exceeding the maximum packet size. Even for

EPDR2 which has double FIFO buffers, write data within the maximum packet size at one time.

After the data is written, write 1 to PKTE in TRG to switch the valid buffer and enable the next

data to be written. Data must not be continuously written to the two FIFO buffers.

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