H8SXSLASH1663 datasheet(869/1158 Pages) RENESAS

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Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 817 of 1102

REJ09B0294-0100

Section 17 I

2C Bus Interface 2 (IIC2)

This LSI has a two-channel I

2C bus interface.

The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus)

interface functions. The register configuration that controls the I2C bus differs partly from the

Philips configuration, however.

Figure 17.1 shows the block diagram of the I2C bus interface 2.

Figure 17.2 shows an example of I/O pin connections to external circuits.

17.1

Features

• Continuous transmission/reception

Since the shift register, transmit data register, and receive data register are independent from

each other, the continuous transmission/reception can be performed.

• Start and stop conditions generated automatically in master mode

• Selection of acknowledge output levels when receiving

• Automatic loading of acknowledge bit when transmitting

• Bit synchronization/wait function

In master mode, the state of SCL is monitored per bit, and the timing is synchronized

automatically. If transmission or reception is not yet possible, drive the SCL signal low until

preparations are completed

• Six interrupt sources

Transmit-data-empty (including slave-address match), transmit-end, receive-data-full

(including slave-address match), arbitration lost, NACK detection, and stop condition

detection

• Direct bus drive

Two pins, the SCL and SDA pins function as NMOS open-drain outputs.

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